4-Bit Counter — Full PDA Flow

01

Design Entry — Mycounter.v

A 4-bit synchronous up-counter with reset

📄 Mycounter.vVerilog

module Mycounter (
    input clk,
    input rst,
    output reg [3:0] out
);

    always @(posedge clk) begin
        if (rst)
            out <= 4'b0000;
        else
            out <= out + 1;
    end

endmodule

💡

Simple by design. This 15-line counter is the perfect first project — small enough to understand every gate in the synthesized netlist, yet complete enough to run through all PDA stages.

02

Simulation — Verify the Counter

Compile & run with Icarus Verilog, view waveforms with GTKWave

📄 Testbench.vVerilog

module Testbench;
    reg clk, rst;
    wire [3:0] out;

    Mycounter uut (.clk(clk), .rst(rst), .out(out));

    initial begin clk = 0; forever #5 clk = ~clk; end

    initial begin
        $dumpfile("count.vcd");
        $dumpvars(0, Testbench);
        rst = 1; #20; rst = 0; #200;
        $finish;
    end

    initial $monitor("Time=%t | rst=%b | out=%d", $time, rst, out);
endmodule

🖥️ Terminal

# Compile RTL + testbench
$ iverilog -o Mycounter Mycounter.v Testbench.v

# Run simulation
$ vvp Mycounter

# View waveforms
$ gtkwave count.vcd

03

Synthesis — RTL to Gates (Yosys)

Map behavioral Verilog to Nangate45 standard cells

📄 yosys_run.tclTcl

# 1. Read source
read_verilog Mycounter.v

# 2. Synthesis
synth -top Mycounter

# 3. Map to Nangate45 library
dfflibmap -liberty Nangate45_typ.lib
abc -liberty Nangate45_typ.lib

# 4. Clean and Write
clean
write_verilog Mycounter_synth.v

# 5. Reports
stat -liberty Nangate45_typ.lib

🖥️ Terminal

$ yosys -s yosys_run.tcl

Synthesis Results

14

Total Cells

4

Flip-Flops

27

Area (µm²)

7

Cell Types

Cell	Count	Role
`DFF_X1`	4	D Flip-Flops (4-bit counter register)
`INV_X1`	1	Inverter
`NOR2_X1`	4	2-input NOR gates
`XNOR2_X1`	1	2-input XNOR gate
`NAND3_X1`	1	3-input NAND gate
`AND2_X1`	1	2-input AND gate
`AOI21_X1`	1	AND-OR-Invert complex gate

Files Generated

File	Origin	Purpose
`Mycounter_synth.v`	🤖 Yosys	Gate-level netlist → input to OpenROAD
`Mycounter_synth.png`	🤖 Yosys	Circuit schematic visualization

04

Physical Design (OpenROAD)

Floorplan → Place → CTS → Route → Layout

📄 Mycounter.sdcSDC

# 10ns clock = 100 MHz
create_clock -name clk -period 10.0 [get_ports clk]

PDA Flow Stages

1

Read Design Load liberty, LEF, synthesized netlist, SDC constraints

2

Floorplan Die: 11×11 µm — Core: 7.7×7.7 µm (2µm margins)

3

Tapcells Insert substrate/well contacts for latch-up prevention

4

Placement Global placement (density 0.5) → detailed legalization

5

Clock Tree Synthesis Balanced clock distribution using BUF_X4 buffers

6

Routing Global route → detailed route on metal layers

7

Reports & Output Timing, area, power → write Mycounter.def + Mycounter.gds

🖥️ Terminal

$ openroad openroad_run.tcl

📁 Complete File Map

File	Origin	Stage	Purpose
`Mycounter.v`	✍️ Written	Design	Synthesizable RTL
`Testbench.v`	✍️ Written	Simulate	Testbench
`yosys_run.tcl`	✍️ Written	Synthesize	Yosys script
`Mycounter.sdc`	✍️ Written	PDA	Timing constraints
`openroad_run.tcl`	✍️ Written	PDA	OpenROAD script
`Mycounter_synth.v`	🤖 Yosys	Synthesize	Gate-level netlist
`Mycounter_synth.png`	🤖 Yosys	Synthesize	Circuit schematic
`Mycounter.def`	🤖 OpenROAD	PDA	Final layout (DEF)
`count.vcd`	🤖 iverilog	Simulate	Waveform dump

Commands Cheat Sheet

# 1. Simulate
$ iverilog -o Mycounter Mycounter.v Testbench.v && vvp Mycounter

# 2. Synthesize
$ yosys -s yosys_run.tcl

# 3. Physical Design
$ openroad openroad_run.tcl