🔄 RTL to PDA Flow

Understanding every file type in the VLSI design flow — from writing Verilog to generating chip layout.

Complete Design Flow

Each stage consumes inputs and produces outputs that feed the next stage

📝
RTL Design
.v
→
🔬
Simulation
.v → .vcd
→
🔍
Coverage
.vcd → .cdd
→
⚙️
Synthesis
.v + .lib →
netlist.v
→
🏗️
PDA
.v + .sdc + .lef
→ .def

📋 File Extensions at a Glance

Extension Full Name Written / Generated Used By
.v Verilog Source ✍️ You write it iverilog, Yosys
.sdc Synopsys Design Constraints ✍️ You write it OpenROAD
.vcd Value Change Dump 🤖 iverilog generates GTKWave, Covered
.lib Liberty Timing Library 📦 Comes with PDK Yosys, OpenROAD
.lef Library Exchange Format 📦 Comes with PDK OpenROAD
.def Design Exchange Format 🤖 OpenROAD generates Layout viewer
1

RTL Design — Writing Verilog

Your design starts here. You write the digital logic in Verilog.
.v design.v
The RTL module — your actual digital logic. Defines inputs, outputs, registers, and behavior using always blocks, assign statements, and state machines.
✍️ You write this
.v testbench.v
The testbench — generates stimulus (clock, reset, test inputs) and monitors outputs. Uses $dumpfile to create waveforms. Not synthesized.
✍️ You write this
// Example: 4-bit counter RTL (counter_4bit.v)
module Mycounter (
    input  clk, rst,
    output reg [3:0] count
);
    always @(posedge clk or posedge rst)
        if (rst) count <= 0;
        else    count <= count + 1;
endmodule
💡
Key rule: The testbench is for simulation only — it's never synthesized. Your design module is what becomes a chip.
2

Simulation — Verify Your Logic

Compile both files with Icarus Verilog to check behavior before hardware.
.v design.v + testbench.v
Input: Both files are compiled together by iverilog. The testbench instantiates your design and drives its ports.
📥 Input
.vcd waveform.vcd
Output: Value Change Dump — records every signal transition over time. Open with GTKWave to visually inspect clock, reset, state, and outputs.
📤 Generated by iverilog/vvp
# Compile design + testbench
$ iverilog -o sim_output design.v testbench.v

# Run simulation (generates .vcd)
$ vvp sim_output

# View waveforms
$ gtkwave waveform.vcd
3

Code Coverage — How Well Did You Test?

Analyze which lines, toggles, and FSM states were exercised during simulation.
.vcd waveform.vcd
Input: The VCD file from simulation. Covered reads this to determine which signals toggled and which code paths were hit.
📥 Input from Stage 2
📊 .cdd
Output: Coverage database. Contains line coverage, toggle coverage, and FSM coverage metrics. Use covered report to view results.
📤 Generated by Covered
# Score coverage
$ covered score -t top_module -v design.v -vcd waveform.vcd -o coverage.cdd

# View coverage report
$ covered report coverage.cdd
4

Synthesis — RTL to Gates

Yosys maps your behavioral Verilog to actual standard cells from the PDK.
.v design.v
Input: Your RTL design. Yosys reads this and converts always blocks to gates and flip-flops.
📥 Input
.lib Nangate45_typ.lib
Input (PDK): Liberty file — describes every standard cell's timing, power, and area. Yosys uses this to pick the best cells for your logic.
📦 From PDK
.v design_synth.v
Output: Gate-level netlist — your design expressed as a network of AND, OR, MUX, DFF cells. This is what gets physically placed on silicon.
📤 Generated by Yosys
# Yosys synthesis commands
yosys> read_verilog design.v
yosys> synth -top module_name
yosys> dfflibmap -liberty Nangate45_typ.lib     # Map flip-flops
yosys> abc -liberty Nangate45_typ.lib            # Map combinational logic
yosys> write_verilog design_synth.v              # Output netlist
yosys> stat -liberty Nangate45_typ.lib           # Print cell count & area
📚
What is a .lib file? It contains detailed models of every standard cell (AND2_X1, DFF_X1, MUX2_X1, etc.) including timing arcs, power consumption, and physical area. Without it, the synthesizer can't map your logic to real gates.
5

Physical Design — Gates to Layout

OpenROAD takes the gate-level netlist and produces a physical chip layout.
.v design_synth.v
Input: Gate-level netlist from synthesis. OpenROAD reads this to know which cells to place.
📥 From Synthesis
.sdc design.sdc
Input: Timing constraints you write — clock period, input/output delays, load capacitance. Tells the tool how fast the chip must run.
✍️ You write this
.lef tech.lef + stdcell.lef
Input (PDK): Physical dimensions — metal layer info (tech) and cell geometry/pin locations (stdcell). Defines the "building blocks" for layout.
📦 From PDK
.def design_final.def
Output: Design Exchange Format — the final chip layout. Contains exact X/Y positions of every cell and metal routing between them.
📤 Generated by OpenROAD
# OpenROAD PDA flow
openroad> read_liberty Nangate45_typ.lib       # Cell timing
openroad> read_lef Nangate45_tech.lef           # Metal layers
openroad> read_lef Nangate45_stdcell.lef        # Cell geometries
openroad> read_verilog design_synth.v           # Gate netlist
openroad> read_sdc design.sdc                   # Timing goals

openroad> initialize_floorplan ...              # Define chip area
openroad> global_placement -density 0.6         # Place cells
openroad> clock_tree_synthesis ...              # Build clock tree
openroad> global_route                          # Route wires
openroad> detailed_route                        # Final routing
openroad> write_def design_final.def            # Output layout!
🎯
What is a .sdc file? You define: (1) Clock period — how fast the chip runs, (2) Input/output delays — timing budget at chip boundaries, (3) Clock uncertainty — margin for jitter. Without SDC, the tool doesn't know if timing passes or fails.

📁 Files You Write vs Files Generated

✍️ YOU WRITE (4 files)

design.v — Your RTL logic
testbench.v — Simulation stimulus
design.sdc — Timing constraints
yosys_run.tcl / openroad_run.tcl — Tool scripts

🤖 TOOLS GENERATE (4 files)

waveform.vcd — Signal dump from sim
coverage.cdd — Coverage report
design_synth.v — Gate netlist
design_final.def — Chip layout

📦 PDK PROVIDES (3 files)

Nangate45_typ.lib — Cell timing/power
Nangate45_tech.lef — Metal layer rules
Nangate45_stdcell.lef — Cell geometry
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