Up/Down Counter with SDC

01

Design Entry — counter.v

A 4-bit bidirectional counter with active-low reset

📄 counter.vVerilog

module up_down_counter (
    input  wire clk,
    input  wire reset_n,     // Active-low reset
    input  wire up_down,     // 1=count up, 0=count down
    output reg  [3:0] count
);

always @(posedge clk) begin
    if (!reset_n)
        count <= 4'b0000;
    else if (up_down)
        count <= count + 1;
    else
        count <= count - 1;
end

endmodule

💡

What's different? Unlike the basic Mycounter, this design adds a up_down direction control and uses active-low reset (reset_n). These are more realistic patterns used in industry designs.

02

Simulation — Verify Counting Behavior

Test both up-counting and down-counting modes

📄 testbench.vVerilog

module tb_up_down_counter;
    reg clk, reset_n, up_down;
    wire [3:0] count;

    up_down_counter dut (.*);

    always #5 clk = ~clk;  // 100 MHz clock

    initial begin
        $dumpfile("counter.vcd");
        $dumpvars(0, tb_up_down_counter);

        clk = 0; reset_n = 0; up_down = 0;
        #20; reset_n = 1;

        // Count UP for 100ns
        up_down = 1; #100;
        // Count DOWN for 100ns
        up_down = 0; #100;
        // Toggle direction
        up_down = 1; #50;
        up_down = 0; #50;
        $finish;
    end

    initial $monitor("Time=%0t | reset_n=%b | up_down=%b | count=%d",
                      $time, reset_n, up_down, count);
endmodule

🖥️ Terminal

# Compile + Run
$ iverilog -o counter counter.v testbench.v
$ vvp counter

# View waveforms
$ gtkwave counter.vcd

03

Timing Constraints — counter.sdc

Learning comprehensive SDC constraints for synthesis-ready designs

📄 counter.sdcSDC

# 1. Create primary clock (100 MHz)
create_clock -name clk -period 10.0 [get_ports clk]

# 2. Set clock uncertainty (jitter + skew margin)
set_clock_uncertainty 0.2 [get_clocks clk]

# 3. Input delays (relative to clock)
set_input_delay 2.0 -clock clk [get_ports {reset_n up_down}]

# 4. Output delays (relative to clock)
set_output_delay 2.0 -clock clk [get_ports count]

# 5. Input transition time
set_input_transition 0.1 [get_ports {clk reset_n up_down}]

# 6. Output load (in pF)
set_load 0.1 [get_ports count]

SDC Constraint Breakdown

Constraint	Value	What It Does
`create_clock`	10 ns period	Defines a 100 MHz clock on the `clk` port
`set_clock_uncertainty`	0.2 ns	Accounts for jitter and skew — adds margin to timing analysis
`set_input_delay`	2.0 ns	Tells tools: inputs arrive 2ns after the clock edge
`set_output_delay`	2.0 ns	Tells tools: outputs must be ready 2ns before the next clock edge
`set_input_transition`	0.1 ns	Specifies how fast input signals switch (rise/fall time)
`set_load`	0.1 pF	Models the capacitive load seen by output pins

📚

Why does this matter? Without SDC constraints, synthesis and PDA tools have no timing target. The clock period defines how fast logic must be, and the input/output delays define the interface timing budget. These constraints are required for any real chip design.

📁 Complete File Map

File	Origin	Stage	Purpose
`counter.v`	✍️ Written	Design	Up/down counter RTL
`testbench.v`	✍️ Written	Simulate	Testbench with direction toggle
`counter.sdc`	✍️ Written	Constraints	Comprehensive timing constraints
`counter.vcd`	🤖 iverilog	Simulate	Waveform dump

Commands Cheat Sheet

# 1. Simulate
$ iverilog -o counter counter.v testbench.v && vvp counter

# 2. View waveforms
$ gtkwave counter.vcd