📘 Project · learning-2

Traffic Light Controller v1

A 3-state traffic light FSM (RED → GREEN → YELLOW) with timer-based transitions. Includes simulation, code coverage, synthesis, and OpenROAD physical design.

Verilog Yosys OpenROAD Covered
📝
RTL
traffic_light.v
🔬
Simulate
iverilog
🔍
Coverage
Covered
⚙️
Synthesize
Yosys
🏗️
PDA
OpenROAD
✅
Layout
DEF
01

Design Entry — traffic_light.v

A 3-state FSM with a counter-based timer (state changes every 4 clock cycles)

📄 traffic_light.vVerilog
module traffic_light (
    input clk, rst,
    output reg red, yellow, green
);
    parameter S_RED=2'b00, S_GREEN=2'b01, S_YELLOW=2'b10;
    reg [1:0] current_state, next_state;
    reg [2:0] count;

    // Sequential: state + timer
    always @(posedge clk or posedge rst) begin
        if (rst) begin
            current_state <= S_RED; count <= 0;
        end else if (count == 3) begin
            count <= 0; current_state <= next_state;
        end else
            count <= count + 1;
    end

    // Next state: RED → GREEN → YELLOW → RED
    always @(*) case (current_state)
        S_RED:    next_state = S_GREEN;
        S_GREEN:  next_state = S_YELLOW;
        S_YELLOW: next_state = S_RED;
        default:  next_state = S_RED;
    endcase

    // Output logic
    always @(*) begin
        {red, yellow, green} = 3'b000;
        case (current_state)
            S_RED:    red    = 1;
            S_GREEN:  green  = 1;
            S_YELLOW: yellow = 1;
        endcase
    end
endmodule
02

Simulation & Coverage

Simulate with Icarus Verilog, analyze code coverage with Covered

🖥️ Terminal
# Compile + Run
$ iverilog -o traffic_light traffic_light.v tb_traffic_light.v
$ vvp traffic_light

# Code Coverage
$ covered score -t traffic_light -v traffic_light.v -vcd traffic.vcd -o traffic.cdd
$ covered report traffic.cdd

# View waveforms
$ gtkwave traffic.vcd

Files at This Stage

File Origin Purpose
traffic_light.v ✍️ Written RTL design
tb_traffic_light.v ✍️ Written Testbench with monitor
traffic.vcd 🤖 Generated Waveform dump
traffic.cdd 🤖 Covered Coverage database
03

Synthesis — RTL to Gates (Yosys)

Map behavioral Verilog to Nangate45 standard cells

📄 yosys_run.tclTcl
read_verilog traffic_light.v
synth -top traffic_light
dfflibmap -liberty Nangate45_typ.lib
abc -liberty Nangate45_typ.lib
opt_clean -purge
tee -o area_report.txt stat -liberty Nangate45_typ.lib
write_verilog traffic_synth.v
show -format dot -prefix traffic_synth

Synthesis Results

20
Total Cells
6
Flip-Flops
45.5
Area (µm²)
8
Cell Types
Cell Count Role
DFFR_X1 5 D Flip-Flops with reset
DFFS_X1 1 D Flip-Flop with set
INV_X1 7 Inverters
MUX2_X1 3 2-to-1 Multiplexers
NAND2_X1 1 2-input NAND
NOR2_X1 1 2-input NOR
AND2_X1 1 2-input AND
XOR2_X1 1 2-input XOR
04

Physical Design (OpenROAD)

Floorplan → Place → CTS → Route → Layout

📄 traffic_light.sdcSDC
create_clock [get_ports clk] -name core_clock -period 10.0
set_input_delay 2.0 -clock core_clock [get_ports rst]
set_output_delay 2.0 -clock core_clock [get_ports red]
set_output_delay 2.0 -clock core_clock [get_ports yellow]
set_output_delay 2.0 -clock core_clock [get_ports green]

PDA Flow Stages

1
Read DesignLoad liberty, LEF, netlist, SDC
2
FloorplanDie: 200×200 µm — Core: 160×160 µm (20µm margins)
3
Tapcells + PDNSubstrate contacts + power distribution network
4
PlacementGlobal (density 0.3) → detailed legalization
5
Clock Tree SynthesisBUF_X4 buffers for clock distribution
6
RoutingPin access → global route → detailed route
7
ReportsTiming, area, and power analysis
💡
Includes PDN. Unlike the simpler counter project, this flow sources Nangate45.pdn.tcl and runs pdngen to build a proper power distribution network before placement.
🖥️ Terminal
$ openroad openroad_run.tcl

📁 Complete File Map

File Origin Stage Purpose
traffic_light.v ✍️ Written Design 3-state FSM RTL
tb_traffic_light.v ✍️ Written Simulate Testbench
yosys_run.tcl ✍️ Written Synthesize Yosys script
traffic_light.sdc ✍️ Written PDA Timing constraints
openroad_run.tcl ✍️ Written PDA OpenROAD script
traffic_synth.v 🤖 Yosys Synthesize Gate-level netlist
traffic_synth.png 🤖 Yosys Synthesize Circuit schematic
area_report.txt 🤖 Yosys Synthesize Cell & area stats
traffic.vcd 🤖 iverilog Simulate Waveform dump
traffic.cdd 🤖 Covered Coverage Coverage database

Commands Cheat Sheet

# 1. Simulate
$ iverilog -o traffic_light traffic_light.v tb_traffic_light.v && vvp traffic_light

# 2. Coverage
$ covered score -t traffic_light -v traffic_light.v -vcd traffic.vcd -o traffic.cdd

# 3. Synthesize
$ yosys -s yosys_run.tcl

# 4. Physical Design
$ openroad openroad_run.tcl