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VyomansLab

Exploring VLSI design from RTL to silicon using 100% open-source EDA tools. Each project walks through simulation, synthesis, and physical design.

5
Projects
3
Full PDA Flows
Nangate45
Target PDK

📂 Projects

Click a project to read the full walkthrough.

🚦 Full PDA ✓
Traffic Light Controller v2
5-state FSM controlling highway & country road intersection with counter-based delays. Full RTL → Synthesis → PDA flow.
Verilog Yosys OpenROAD Nangate45
42 cells 68.9 µm² 85% util 0 DRC
📦 t_final.def · t_synth.v · area_report.txt
→
🚥 Full Flow ✓
Traffic Light Controller v1
3-state traffic light FSM (RED → GREEN → YELLOW) with timer-based transitions. Includes simulation, coverage, synthesis, and OpenROAD PDA.
Verilog Yosys OpenROAD Covered
20 cells 45.5 µm² 58 lines RTL
📦 traffic_synth.v · traffic_synth.png · traffic.vcd
→
🔢 Full Flow ✓
4-Bit Counter — Full PDA
Simple 4-bit synchronous counter taken through the complete VLSI flow: simulation → coverage → Yosys synthesis → OpenROAD floorplan, placement & routing.
Verilog Yosys OpenROAD Coverage
14 cells 27 µm² 15 lines RTL
📦 Mycounter.def · Mycounter_synth.v · Mycounter_synth.png
→
⏱️ Sim + SDC
Counter with Timing Constraints
Extended counter design with SDC timing constraints. Explores clock definition, input/output delay specifications for synthesis-ready designs.
Verilog SDC Constraints
learning_2 SDC constraints
📦 counter.sdc · counter.vcd
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🧪 Simulation
4-Bit Counter — Simulation
First-principles counter design focusing on Icarus Verilog simulation and code coverage analysis with Covered. The starting point for learning Verilog.
Verilog Icarus Verilog Covered GTKWave
icarus_codes VCD waveform
📦 count.vcd · Mycounter.cdd

🔧 Toolchain

All projects use these open-source tools:

📝
Icarus Verilog
RTL Simulation
📊
GTKWave
Waveform Viewer
🔍
Covered
Code Coverage
⚙️
Yosys
Logic Synthesis
🏗️
OpenROAD
Physical Design
🔬
Nangate45 PDK
Standard Cell Library